This invention relates to an on-chip, dual polarity, high voltage multiplier and, more particularly, to a voltage multiplier having an extended operating temperature, as high as 150.degree. C.
As used throughout, the following two definitions apply:
"Rise time" is the time taken by the positive voltage multiplier to increase its output voltage from approximately the 10% level to the 90% level of the final voltage.
"Fall time" is the time taken by the negative voltage multiplier to decrease its output voltage from approximately the 10% level to the 90% level of the final voltage.
To be competitive in the marketplace, a non-volatile memory device is now required to be a "5 volt only" device. This means that the memory device, for example a non-volatile random access memory (NVRAM), which typically requires multiple external power supplies (providing +5 volt, +22 volt and -22 volt voltages for read, write and erase operations, respectively) should have the capability to generate the high write and erase voltages, on chip, by utilizing a single 5 volt external power supply. One method of on-chip high-voltage generation is by means of the voltage multiplier technique. One such prior art voltage multiplier is shown in FIGS. 1A and 1B which represent circuits for generating a low negative voltage and a high positive voltage, respectively.
Referring to FIG. 1A, V.sub.g represents the ground connection and V.sub.out is the voltage output of the negative multiplier. V.sub.out &lt;&lt;V.sub.g. C.sub.1, C.sub.2 - - - C.sub.n are coupling capacitors and Q.sub.1, Q.sub.2 - - - Q.sub.m are rectifying elements (or diodes). In this prior art voltage multiplier arrangement, the capacitors were permanent capacitors (i.e. their operation is not dependent on the polarity of the voltage applied across their plates) and the rectifying elements were diode-connected enhancement mode metal-oxide-semiconductor (MOS) transistors.
Referring to FIG. 1B, V.sub.cc here represents the input power supply voltage, typically 5 volts and V'.sub.out is the voltage output of the positive voltage multiplier. V'.sub.out &gt;&gt;V.sub.cc. As in FIG. 1A, C'.sub.1, C'.sub.2 - - - C'.sub.n and Q'.sub.1, Q'.sub.2 - - - Q'.sub.m represent coupling capacitors and diodes, respectively.
.phi..sub.1 and .phi..sub.2 shown in FIG. 1A and .phi.'.sub.1 and .phi.'.sub.2 shown in FIG. 1B designate two clock pulses, of the type shown in FIG. 2, having a fixed amplitude and in antiphase with each other. These pulses are applied to the successive nodes of the diode-chain via the coupling capacitors. The amplitude of these clock pulses is typically about 5 volts.
The output nodes V.sub.out and V'.sub.out of the negative and positive voltage multipliers shown in FIGS. 1A and 1B are connected together to generate high positive and low negative voltages at the same (output) node. This ability is essential for an on-chip voltage multiplier since devices on an integrated circuit chip, such as NVRAMs, invariably require that the same node of the voltage multiplier go both positive and negative for purposes of programming the device.
In actual construction of the on-chip dual polarity voltage multiplier, it is necessary that the MOS diode elements Q.sub.1, Q.sub.2 . . . Q.sub.m of the negative multiplier be located in regions of the substrate isolated from the remainder of the chip. This is necessary because the negative voltage multiplier pulls the isolated region negative with its output voltage. If isolation was not used, turning on of the negative voltage multiplier would interfere with the functioning of the peripheral circuits. The isolated region may be either a diffused well or an isolated epitaxial region formed on the substrate. For example, if the diodes Q.sub.1, Q.sub.2 - - - Q.sub.m are n-channel MOS devices, the diffused well approach will utilize an n-type substrate in which p-wells are formed. The corresponding isolated epitaxial region approach, which is disclosed in the copending application Ser. No. 410,674, entitled "Method of Fabricating An I.C. Voltage Multiplier" by the present inventor and assigned to the assignee of the present invention, is shown in FIG. 3. This approach involves using an n-type substrate 10 (typically, single crystal silicon) having thereon a p-type epitaxial silicon layer (hereafter, p-epi layer) 11 flanked by deep N.sup.+ diffusions 12. The diffusions 12--12 isolate the p-type epitaxial layer 11 from the remainder of the integrated circuit.
Regardless of whether the diffused well or isolated epitaxial region approach is chosen, the dual polarity voltage multiplier suffers from (1) a slow response (i.e. long fall time) of the negative multiplier due to a large substrate to p-epi/p-well junction capacitance C.sub.ss and (2) rapid deterioration of the negative voltage multiplication scheme at elevated temperatures due to the turning on during the negative cycle of the clock pulses .phi..sub.1 and .phi..sub.2 of parasitic transistors associated with the MOS devices. To fully understand these problems, reference is made to FIG. 3 wherein is shown, in cross-sectional representation, the diode Q.sub.2 (of FIG. 1A). The diode Q.sub.2 shown in FIG. 3 is an n-channel MOS transistor and comprises a conductive polysilicon gate 13 and highly doped n.sup.+ drain and source regions 14 and 15, respectively. A relatively thin silicon dioxide (gate oxide) 16 insulates the polysilicon gate 13 from the underlying p-epi region 11. Transistor Q.sub.2 further includes metal contacts 17, 18, and 19 making electrical contact, respectively, with drain 14, source 15 and gate 13. For consistency with FIG. 1A, gate 13 and drain 14 of transistor Q.sub.2 shown in FIG. 3 are connected together and this common point is connected to the (source of) transistor Q.sub.3 and one plate of coupling capacitor C.sub.2 and the source 15 of Q.sub.2 is connected to coupling capacitor C.sub.1 and transistor Q.sub.1.
In operation, a nominal 5 volt potential is always applied to the substrate 10. For the low negative voltage multiplication to take place the p-epi layer 11 to n-substrate 10 junction capacitance C.sub.ss needs to be charged. However, because the parasitic bipolar transistor formed by the n.sup.+ drain 14, the p-epi region 11 and the n-substrate 10 is turned on whenever the n.sup.+ region 14 is pulled more negative than the p-epi region 11, the effective capacitance of the p-epi to substrate 10 junction C.sub.eff will be increased by a factor equal to the current gain B of the parasitic transistor mentioned hereinabove. In other words, C.sub.eff is equal to B.times.C.sub.ss. The gain B is inversely proportional to the thickness of the p-epi layer 11 and typically is high, of the order of one hundred or more. As a result of this large effective capacitance, the p-epi to n-substrate capacitor will be charged rather slowly and thereby the fall time of the negative voltage multiplier will be undesirably increased.
The deterioration in the performance of the negative voltage multiplier with increasing temperature referred to hereinabove is due to the relative ease of turning on of the parasitic bipolar transistor 14-11-10 (FIG. 3) during the negative cycle of the waveforms .phi..sub.1 and .phi..sub.2 which drive the multiplier. As temperature increases, the built-in potential of the parasitic bipolar transistor pn junctions will decrease, making this parasitic transistor turn on more easily. Consequently, the parasitic transistor will compete with the MOS transistor Q.sub.2 and will transfer off more and more voltage multiplier output current to the substrate 10 via the parasitic transistor rather than enabling the output current to be transferred to the successive stages of the negative voltage multiplier. As a result of this competition between the parasitic bipolar transistor and the MOS transistor, the negative voltage multiplication will deteriorate.
The positive voltage multiplier in the dual polarity voltage multiplier pair (shown in FIG. 1B) does not suffer from the above problems associated with the negative multiplier since the parasitic transistors associated with the MOS diodes that are utilized in the construction of the positive voltage multiplier are not turned on. This is because the p-epi region similar to 11 in this case is always at least 5 V more negative than any of the n.sup.+ regions similar to 14 (FIG. 3). Consequently, the waveforms .phi..sub.1 and .phi..sub.2 (which are .+-.5 V) can never bring the n.sup.+ region to a more negative potential than the p-epi region. Since the parasitic transistors are not turned on, there is no shunting of current from the positive multiplier output node to the substrate. Also, since there is no need for charging up the p-epi layer to substrate 10 capacitance, the rise time of the positive voltage multiplier is not affected.
One way of solving the above problems associated with the negative voltage multiplier is to connect the output of the negative multiplier V.sub.out (FIG. 1A) to the p-epi well region 11 and thereby reducing the current going to substrate 10 (FIG. 3). However, this is not practical, since the output node V.sub.out of the negative multiplier is connected to the output node V'.sub.out of the positive multiplier and this common node goes both positive and negative during the operation of the positive multiplier and negative multiplier respectively. As a result, whenever the positive output of this common node is applied to the p-epi well region 11, the pn junction (isolation diode) formed by the p-epi region 11 and the n-substrate 10 will be forward biased, thereby limiting the positive voltage to an isolation diode drop higher than the bias on the n-substrate 10. Consequently, the positive voltage multiplier operation will be severely inhibited.